High-level Synthesis of Scalable Architectures for Iir Filters Using Parameterized Mcm's

We describe the high-level synthesis of scalable 1 parallel architectures implementing in niteimpulse response (IIR) lters using multi-chip module (MCM). Our approach is based on a new class of parallel schedules for computing mth-order IIR lters, called regular schedules. The simplicity of the regular schedules facilitates characterization of their inter-processor communications, which is generally di cult to express for parallel algorithms. The characterization of inter-processor communications of the regular schedules enables us to generate instruction-level behavior of the design that can be easily mapped onto MCM-based architectures. We illustrate the use of the regular schedule in algorithmic-level synthesis of MCM-based parallel application-speci c processors implementing the fth-order elliptic wave lter benchmark. Our approach yields a scalable performance measured in the lter's sample rate on both multiple-bus architectures and mesh architectures, which is not known to have been achieved by previously published approaches. keywords: High-level synthesis of parallel architectures, scalable scheduling techniques, high-performance in nite-impulse response (IIR) lters, MCM-based implementations.